The present disclosure relates to the fabrication of integrated circuit transistors, and in particular, to the fabrication of silicon channels on silicon-on-nothing (SON) devices.
In the semiconductor industry there is a continuing trend toward manufacturing integrated circuits (ICs) with higher densities. Smaller feature sizes, smaller separations between features and more precise feature shapes are desired in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes, as well as the surface geometry of various other features (e.g., corners and edges). The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher cost efficiency in IC fabrication by providing more circuits on a die and/or more die per semiconductor wafer.
In the case of a conventional MOS transistor in “bulk” technology, active zones of the device are directly implanted in a mass (“bulk”) of thick silicon forming the silicon substrate. The presence of a thick substrate that is electrically continuous with the active superficial layers, however, induces parasitic phenomena therein, and makes them sensitive to electrical disturbances (for example, leakage currents toward the substrate).
A desirable feature of transistors fabricated using silicon-on-nothing (SON) technology, by comparison with the conventional “bulk” transistors, is the presence of a thin embedded dielectric layer, which insulates the conductive channel of the transistor from the substrate and provides for better control of parasitic effects. SON technology also makes it possible to produce transistors with dynamic properties that are superior to those of the conventional CMOS technology and that are characterized by lower power consumption.
There is a need for circuits that are capable of simultaneously integrating components whose functions involves electrical properties specific to “bulk” devices, and components performing faster functions and thus involving electrical properties specific to SON. Therefore, there is a need to integrate these two types of devices on a single substrate.